Thanks to your overwhelming response to my appeal for information about CPU core frequencies in M3 Ultra and M5 base chips, this article updates the data to cover those new models in addition to all previous M-series chips.

Performance (P) and Efficiency (E) CPU cores in Apple silicon Macs are run at a range of different frequencies so they can deliver optimum performance with a minimum power and energy use. Cores are grouped into clusters of 2-6, and macOS sets the frequency of each cluster according to workload, Quality of Service, power mode and thermal status. Maximum frequencies differ according to the family, variant within that family, and between E and P cores. Current values are:

• M1 E 2064 MHz or 2.1 GHz; P 3228 MHz or 3.2 GHz;
• M2 E 2424 MHz or 2.4 GHz; P 3696 MHz or 3.7 GHz;
• M3 E 2748 MHz or 2.7 GHz; P 4056 MHz or 4.1 GHz;
• M4 E 2892 MHz or 2.9 GHz; P 4512 MHz or 4.5 GHz.
• M5 E 3048 MHz or 3.0 GHz; P 4608 MHz or 4.6 GHz (base variant only).

As Pro and Max variants may have higher frequencies than base variants, it’s likely that future M5 Pro or M5 Max chips will be able to run their P cores at a higher maximum frequency than today’s base M5 chip.

The full table of frequencies reported by powermetrics is:

This is available for download as a Numbers spreadsheet and in CSV format here: mxfreqs1025

Earlier this year I published a detailed analysis of frequencies in the M1 to M4 families. The only addition to those is the M3 Ultra, whose frequencies are the same as those of the M3 Max, so they haven’t changed. The remainder of this article concentrates on the base variant in each family, from M1 to M5, the chips that power the most popular models and set the standard for what most folk will experience.

Frequency range

Over the last five years and five families of chips, their frequencies have increased steadily, as shown in the charts below. Each bar in those charts spans the range of frequencies from minimum (idle) to maximum, for the base variant in that family.

Idle frequency in E cores has risen from 600 MHz to 972 MHz, a rise of over 60%, and their maximum frequency has risen from 2064 MHz to 3048 MHz, a rise of nearly 50%.

P cores have seen more substantial change. Their idle frequency has risen from 600 MHz to 1308 MHz, a much larger rise of nearly 120%, and their maximum frequency has risen from 3204 MHz to 4608 MHz, just under 50%. The M5 is notable for its greater rise in idle frequency, and lesser rise in maximum frequency.

Frequency steps

Rather than macOS set an arbitrary frequency, it selects one from a list of steps that are distinctive to that family and variant. Looking at the table of frequency steps it might be easy to assume those numbers are chosen arbitrarily, but when expressed appropriately I think you can see there’s more to them.

To look at frequency steps and the frequencies chosen for them, let me explain how I have converted raw frequencies to make them comparable.

First, I work out the steps as evenly spaced points along a line from 0.0, representing idle, to 1.0, representing the core’s maximum frequency. For each of those evenly spaced steps, I calculate a normalised frequency, as
(Fmax – Fstep)/(Fmax – Fidle)
where Fidle is the idle (lowest) frequency value, Fmax is the highest, and Fstep is the actual frequency set for that step.

For example, say a core has an idle frequency of 500 MHz, a maximum of 1,500 MHz, and only one step between those. Its steps will be 0.0, 0.5 and 1.0, and if the relationship is linear, then the frequency set by that intermediate step will be 1,000 MHz. If it’s greater than that, the relationship will be non-linear, tending to a higher frequency for that step. The following charts compare those normalised frequencies with steps evenly spaced between idle and maximum frequencies.

This chart shows normalised frequencies and steps for E cores in base M1 and M5 chips, the latter in red. It shows how, over those five years, the number of steps (available frequencies) has increased. In the M1, the frequency selected in the middle of its five steps was half-way between idle and maximum. Not only does the M5 have more intermediate frequencies available, six instead of three, but frequencies used in the upper half of its steps are higher than in the M1 (when normalised).

This tends to boost higher frequencies used for running threads that can’t be accommodated on P cores, while running background threads at slightly lower frequencies than would be expected when at frequencies close to idle, as they are.

These curves have undergone evolution across different families, as shown here in a composite of the curves for all five families. The red curve of the M5 deviates more from the M1’s straight line of identity than any of the others, particularly at the top end.

The equivalent comparison between frequencies of P cores in M1 and M5 chips shows a different picture. The M1 is again the simpler, being linear until it reaches a step of 0.8, while the M5 has higher frequencies in all except the top few values.

Shown here alongside curves for all earlier families, the red curve for the M5 has higher frequencies for every step apart from the last few.

Taken with the trends seen in the frequency ranges (bar charts above), these demonstrate that the M5 is designed to improve performance by increasing the frequencies used to run threads with higher Quality of Service, as opposed to background threads.

Conclusions

• CPU core frequencies in the M3 Ultra are the same as the M3 Max.
• The base M5 continues the trend for higher frequencies in both E and P cores, with a marked rise in P core idle frequency.
• More subtle changes in intermediate frequencies boost them for higher frequencies of E cores, where they’re likely to improve performance of threads overflowed from P cores.
• Intermediate core frequencies continue to be selected to optimise performance and power use.